Conventional source-synchronous receivers receive input data synchronously with an input clock. A separate output clock provides the signals required for outputting the received data. Such a source synchronous receiver may be implemented using a circular FIFO queue that includes a number of data registers for holding the received data. An input pointer, advanced by an input clock, steers the data received from the bus to the proper register, e.g., first data is directed to go into a first register, second data into a second register, and so on. A multiplexer is connected to the data storage device and sends data from a selected data register at the proper time to an output latch. The multiplexer and the output latch typically receive their signals from the same output clock. The input clock signal, however, often has a varying phase and frequency relationship with respect to the output clock.
Progressively higher clock frequencies used in processors and on busses have placed greater demands on source-synchronous receivers to accommodate longer delays, up to several clock states or periods, and wider ranges of variations in clock instantaneous frequency and phase shift. The same amount of time delay encompasses more clock states at higher frequencies than at lower frequencies. Thus, the average overall delay in the system will depend on the system frequency and configuration. Short-term phase and frequency variations also occur. These variations must also be accommodated or compensated for in order to maintain a predictable or constant data availability time. In other words, the elapsed time or the number of clock states from the time data is called for to the time when that particular data is made available at the output of the source synchronous receiver should be a predictable system behavior in spite of frequency and phase variations that occur between the time that data is called for and the time that the called-for data is present at the input of the source synchronous receiver.